1. Field of the Invention
The present invention relates generally to semiconductor memory devices having error checking and correcting circuits (ECC) and, more particularly, to testing memory devices including ECC in which complete checker pattern data are written into the memory cells to be tested. The present invention has particular applicability to an electrically erasable programmable read only memory.
2. Description of the Background Art
Recently, the storage capacity of a semiconductor memory is substantially increased due to a higher degree of integration thereof. Defects in memory cells are more liable to occur with a higher degree of integration of the memory. Two methods have been known as countermeasures for the defects occurring in the memory cells; that is, the one is by employing a redundancy circuit, and the other is by employing an error checking and correcting (hereinafter referred to as "ECC") circuit. In the redundancy circuit method, spare memory cell rows or columns are provided in advance in a semiconductor memory to be electrically exchanged for memory cell rows or columns where defective memory cells exist. More specifically, the defective memory cell rows or columns are replaced by the spare memory cell rows or columns. In the ECC circuit method, errors which occur in data signals read out of the memory cells are checked. When the errors exist, error data thereof is automatically corrected. A brief description will be given on the ECC.
The ECC is provided to achieve high reliability of stored data in the semiconductor memory such as an electrically erasable programmable read only memory (hereinafter referred to as "EEPROM"). The EEPROM to which the ECC is employed comprises a memory cell for ECC as well as a memory cell for data storage. As an example of the ECC, a single bit error correction (hereinafter referred to as "SEC") is known. In a case where erroneous bits exist in data bits and ECC bits both having a predetermined data length, the SEC circuit is provided to detect and correct the erroneous bits. A description as to the ECC circuit is given in, for example, a paper entitled "A 70-ns Word-Wide 1-Mbit ROM With On-Chip Error-Correction Circuits" (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL SC-20, NO. 5, OCTOBER 1985). In addition to this SEC, an ECC circuit is also known which can detect and correct erroneous bits of 2 or 3 bits in order to obtain data signals having higher reliability.
In the case of single bit error correction (SEC), for example, where a bit length of a data word is represented by m, and that of an ECC word is represented by k, the m and k are required to satisfy the following inequality. EQU 2.sup.k- 1.gtoreq.m+k
A comparison of the data bit length m and the ECC bit length k to be integer values, based on the above inequality, is shown in Table 1.
TABLE 1 ______________________________________ Data bit length (m) 4 8 16 32 64 ______________________________________ ECC bit length (k) 3 4 5 6 7 ______________________________________
FIG. 4A is a circuit block diagram of a conventional EEPROM. A description as to the EEPROM shown in FIG. 4A is disclosed in, for example, U.S. Pat. No. 4,811,294. In addition to this, a description as to a more detailed circuit of the memory cell is disclosed in, for example, U.S. Pat. No. 4,805,151. Referring to FIG. 4A, this EEPROM comprises a memory array 1 formed of a memory array 1a for storing data and a memory array 1b for storing ECC data, a Y gate circuit 6 for selecting a bit line BL, a sense amplifier 8 for amplifying data signals stored in the memory arrays 1a and 1b, a generation circuit 9 for generating ECC data in response to input data supplied via an input/output buffer 107, and an ECC circuit 7 for checking and correcting data stored in the memory array 1a based on data stored in the memory array 1b. The X decoder 3 selects a word line WL in response to X address signals X.sub.O -X.sub.n applied via an X address buffer 2. A Y decoder 5 controls the Y gate circuit 6 in response to Y address signals Y.sub.O -Y.sub.m applied via a Y address buffer 4. The Y gate circuit 6 selects a bit line BL.
A read/write control circuit 114, an erase/program control circuit 115, and a read control circuit 117 are provided to control this EEPROM. These control circuits 114, 115 and 117 control data reading/writing/outputting and the operation of the EEPROM in response to a chip enable signal CE, an output enable signal OE, a write enable signal WE and the like, which are externally applied to a control signal buffer 113.
A column latch/high voltage switch circuit 118 and a word line high voltage switch circuit 119 are provided at the periphery of the memory arrays 1a and 1b. The column latch/high voltage switch circuit 118 latches data D0-D7 to be stored in the memory cell array 1a and ECC data P1-P4 to be stored in the memory array 1b. A higher voltage developed in accordance with the latched data is applied to the bit line in programming operation and to a control gate line in erasing operation. The word line high voltage switch circuit 119 applies a high voltage to the word line in either the programming operation or the erasing operation.
One memory cell 101 comprises a selecting transistor 102 and a storing transistor 103. The transistor 103 comprises a floating gate 105 for storing data. The transistor 102 has its source connected to the bit line BL and its gate connected to the word line WL. The transistor 103 has a control gate connected to the control gate line CGL. The memory arrays 1a and 1b are both formed of a large number of memory cells 101.
In data writing, input data D0-D7 are externally supplied to the input/output buffer 107 and the data D0-D7 are supplied to the column latch/high voltage switch circuit 118 via the Y gate circuit 6. The data latched in the column latch/high voltage switch circuit 118 are stored as the data D0-D7 in the memory array 1a. Meanwhile, the ECC data generation circuit 9, to be described later with reference to FIG. 6, generates the ECC data P1-P4 in response to the input data D0-D7. The data P1-P4 are supplied to the column latch/high voltage switch circuit 118 via the Y gate circuit 6, and the latched data are stored as the ECC data P1-P4 in the memory array 1b.
In data reading, the data stored in the respective memory arrays 1a and 1b are supplied via the Y gate circuit 6 to the sense amplifier 8. The data D0-D7 and ECC data P1-P4 amplified by the sense amplifier 8 are supplied to the ECC/circuit 7 to be subject to error checking and correcting processing therein. The processed data is outputted externally via the input/output buffer 107.
As can be understood in the above description, it should be noted that the ECC data P1-P4 ar internally generated and processed in the EEPROM. Therefore, it can be mentioned that one byte of data is formed of data bits D0-D7 and ECC bits P1-P4. A one byte data configuration is shown in FIG. 4B.
FIG. 5 is a sectional view showing a sectional structure of a memory cell for EEPROM provided on a semiconductor substrate. Referring to FIG. 5, the memory cell 101 comprises the transistor 103 for storing -data and the selecting transistor 102. The transistor 103 comprises the floating gate 105, a control gate 106, and source and drain regions 108 and 104 formed in a p type silicon substrate 111. The transistor 102 comprises a gate 110, and source and drain regions 104 and 109 formed in the substrate 111. The gates 105, 106 and 110 are isolated from one another by an insulating layer (not shown) formed on the substrate 111.
Data writing is carried out by storing a positive or negative charge in the floating gate 105. That is, the storing of the charge causes a change of a threshold voltage of the transistor 103 and thus storing of data "0" or "1". Since a portion of the insulating layer, sandwiched between the n.sup.+ region 104 and the floating gate 105, is formed of a very thin oxide film, electrons can be stored or discharged in the floating gate 105 through this oxide film portion by employing a tunnel effect.
In erasing operation, electrons are injected into the floating gate 105 so as to increase the threshold voltage of the transistor 103. This operation, corresponding to storage of the data "1", brings the bit line BL to a ground potential, and application of a higher voltage to the word line WL and the control gate line CGL enables data erasing. In programming operation, electrons are extracted from the floating gate 105 so as to decrease the threshold voltage of the transistor 103. This operation, corresponding to storage of the data "0", holds the control gate line CGL at the ground potential, and is carried out by application of a higher voltage to the word line WL and to the bit line BL.
FIG. 6 is a circuit diagram showing an example of the ECC data generation circuit 9 shown in FIG. 4A. Referring to FIG. 6, the ECC data generation circuit 9 comprises EXOR gates 91 to 94 connected to selectively receive the input data D0 to D7. The EXOR gates 91 to 94 output the respective ECC data P1 to P4 in response to the input data D0 to D7. When data (0, 1, 0, 1, 0, 1, 0, 1) are supplied as the input data D0 to D7, for example, data (0, 1, 1, 1) are obtained as the ECC data P1 to P4. The ECC data P1 to P4 are stored in desired memory cells provided in the memory arrays 1a and 1b with the input data D0 to D7, as described above.
An EXOR gate having a plurality of inputs generates output signals indicating logic "1" when supplied with an odd number of input signals exhibiting only one of logics "1" and "0", while it generates output signals exhibiting logic "0" when supplied with an even number of input signals exhibiting only one of logics "1" and "0".
FIG. 7 is a circuit diagram of an example of the ECC circuit 7 shown in FIG. 4A. Referring to FIG. 7, the ECC circuit 7 comprises EXOR gates 121-124 connected to selectively receive data D0'-D7' and P1'-P4' read from the memory arrays 1a and 1b, inverters 131-134 for inverting output signals of the EXOR gates 121-124, AND gates 141-148 connected to selectively receive output signals of the EXOR gates 121-124 and of the inverters 131-134, and EXOR gates 151-158 connected to sequentially receive output signals of the read data D0'-D7' and of the AND gates 141-148. Error-corrected data D0-D7 are obtained via the EXOR gates 151-158.
An operation of the ECC circuit 7 shown in FIG. 7 will now be described in each of the cases that a defect occurs/does not occur in one of the memory cells storing the data D0'-D7' and P1'-P4'. First of all, in the case of no defect occurring in the memory cell, the read data D0'-D7' and P1'-P4', which are the same as the written data D0-D7 and P1-P4, are outputted from the memory arrays 1a and 1b. The EXOR gates 121-124, corresponding to the respective EXOR gates 91-94 in the ECC data generation circuit 9 shown in FIG. 6, are connected to selectively receive the data D0'-D7'. The EXOR gate 91 shown in FIG. 6 is, for example, connected to receive the data D0-D3, while the EXOR gate 121 shown in FIG. 7 is connected to receive the data D0'-D3'.
In addition, the EXOR gate 121 is connected to receive the read data P1' corresponding to the ECC data P1 outputted from the EXOR gate 91. Therefore, the EXOR gate 121 is supplied with an even number of data "1" in the case of no defect existing in the memory cell. The other EXOR gates 122-124 are connected in the same manner as the EXOR gate 121. Therefore, the EXOR gates 121-124 output output signals M1-M4 of a low level in response to an even number of the same data "1". As a result, the inverters 131-134 output signals M1-M4 of a high level. The AND gates 141-148 output signals of the low level in response to these signals M1-M4 and M1-M4. Accordingly, the EXOR gates 151-158 output the read data D0'-D7' as the correct data D0-D7 without being inverted.
The next description will be given on the operation in the case that a defect exists in one of the memory cells storing the read data D0'-D7' and P1'-P4'. Such case will be described as an example that the data "0" is read out as the data D3, which is to be "1" correctly. In this case, the EXOR gate 121 is supplied with data (0, 1, 0, 0, 0) as the input data, while the EXOR gate 124 is supplied with data (1, 0, 0, 1, 1) as the input data. Therefore, the EXOR gates 121 and 124 output the signals M1 and M4 of the high level. Meanwhile, the EXOR gates 122 and 123 output the signals M2 and M3 of the low level because they are not supplied with the data D3'. Therefore, only the AND gate 144 outputs a signal of the high level in response to supplied input data (1, 1, 1, 1), while the other AND gates 141-143 and 145-148 all output signals of the low level. The EXOR gate 154 has one input receive a high level signal outputted from the EXOR gate 144. Thus, the EXOR gate 154 outputs data inverted from the read data D3' as the data D3. Since the other EXOR gates 151-153 and 155-158 each have one input supplied with a signal of the low level, these gates output read data D0'-D2, and D4'-D7' as they are without being inverted.
As has been described, even if the data, inverted due to the defect in the memory cell, is read out, the performance of the ECC circuit 7 shown in FIG. 7 allows an error to be checked and corrected and thus enables the correct data to be outputted.
A description will be given on the necessity of confirmation of writing and reading of alternating bit testing pattern data in a preshipment test to be carried out before the semiconductor memory is put on the market. This alternating bit testing pattern is often called "checker pattern". An example of the checker pattern data is shown in FIG. 9A. In the EEPROM, for example, defects in the memory cells are caused by a short circuit of the floating gate. In the EEPROM, memory cells of one byte, adjacent to one another, are provided on the semiconductor substrate. A defect caused by the short of the floating gates each included in two adjacent memory cells is called a floating short. If such a defect occurs, data written in one of the memory cells is also written in the other. In order to detect the presence of such a defect, data writing/reading need be confirmed by writing data having opposite signal levels in the adjacent memory cells and by reading out the written data. Therefore, data (0, 1, 0, 1, 0, 1) are provided as checker pattern data D0-D7 in the test of the EEPROM shown in FIG. 4A.
FIG. 8A is a circuit diagram showing connection between conventional bit lines 30-41 and data lines 10-21 of an EEPROM. The EEPROM includes in general two or more memory array sections. For example, an EEPROM having a 64Kbit- storage capacitance includes 32 memory array sections. A description will be given, for simplification, on circuits associated with two memory array sections 201 and 202 provided in the EEPROM. Referring to FIG. 8A, the bit lines 30-41 connected to the memory array 201 are connected respectively to the data lines 10-21 via a Y gate circuit 6a. Each of transistors constituting the Y gates circuit 6a has its gate connected to receive an output signal Y1 from the Y decoder. Data D0-D7 and P1-P4 are written in the memory array 201 via the respective bit lines 30-41 and then are read out of the memory array 201. Another circuit handling another word which is, connected to a Y gate circuit 6b and is also shown in FIG. 8A, is connected in the same manner as the Y gate circuit 6a. The data lines 10-21 are connected to the ECC data generation circuit 9 shown in FIG. 6. Therefore, the data lines 10-17 are supplied with the data D0-D7 to be written, while the data lines 18-21 are supplied with the ECC data P1-P4 to be written.
An interconnection diagram (a plan view) for the interconnection shown in FIG. 8A is shown in FIG. 8B. FIG. 8B shows the connections of the memory array section 201 and sense amplifier 8 to interconnections 10-21. The data D0-D7 and P1-P4 are transmitted via the respective interconnections 10-21. Interconnections M0-M11 are connected between the memory array section 201 and the interconnections 10-21. The interconnections 10-21 are connected through holes TH to the interconnections M0-M11, respectively. Interconnections S0-S11 are connected between the sense amplifier 8 and the interconnections 10-21. The interconnections 10-21 are connected through holes to the interconnections S0-S11, respectively.
Since the bit lines 30-41 and the data lines 10-21 are sequentially connected via the Y gate circuit 6a in the conventional circuit connection, as described above, the following inconvenience occurs that a test employing the checker pattern data cannot be stored in all cells of each byte. Storage of the alternating bit testing pattern is necessary for identifying coupling between cells or shorts between signal lines. Such a coupling or shorting becomes apparent when the alternating bit testing pattern stored in the memory cells in the test is read out.
In the case that the above data D0-D7 are supplied as the checker pattern data, for example, data (0, 1, 1, 1) is outputted as the ECC data P1-P4 from the ECC data generation circuit 9 shown in FIG. 6. That is, although the bit pattern shown in FIG. 9A, for example, should be employed as the checker pattern data, the bit pattern shown in FIG. 9B is obtained in practice. This means that data of opposite signal levels cannot be written in the adjacent memory cells storing the ECC data P2-P4. Thus, there is a problem that the data of the opposite signal levels cannot be written in all the adjacent memory cells even by employing the checker pattern data, and hence the complete test cannot be carried out. In this case, an additional writing cycle is required to write the checker pattern data in the remaining memory cells for storing the ECC data. Therefore, additional operations are required and a testing procedure becomes complicated.